Summary
Overview
Work History
Education
Skills
Accomplishments
Certification
Temporary Employment
Visa
References
Projects
Hobbies: Pencil sketching
Languages
Generic

Rahul Siddalingappa

Kensington,WA

Summary

A dedicated and skilled FPGA Engineer with extensive experience in design, testing, and maintenance of embedded systems. Proficient in a diverse range of platforms, languages, and FPGA technologies. Demonstrated expertise in the development and verification of complex systems within the aerospace and defense sectors, showcasing strong competencies in utilizing tools like VHDL, Verilog, UVMF, and various simulation and synthesis tools. Adept at working independently on intricate projects, as well as collaborating effectively within a team. Completed a Master's program for advancing skills in embedded systems through, with a keen focus on practical applications in IoT and embedded technology. Proven ability to innovate and drive projects to successful completion, underscored by strong analytical and problem-solving abilities.

Overview

5
5
years of professional experience
2
2
Certification

Work History

Fpga Engineer

Collins Aerospace
02.2019 - 02.2022

This company is an aerospace and defense manufacturer, and I worked as a Validation and Verification engineer.

Universal IO: Involved in the verification of an aerospace-based Universal Input Output bridge. Utilized DO-254 compliant UVMF (SV) test-benches.

  • Designed UART, ADC, API, and I2C BFM models.
  • Developed a verification environment for Smartfusion2 FPGA, integrating UVMF framework and YAML scripts.
  • Successfully verified 104 requirements using QuestaSim, identifying 61 design issues.

Generator monitor: Focused on verifying a military-based on-ground generator unit monitor.

  • Led the creation of the verification environment, integrating eNVM and developing Inter-FPGA, RS485 BFM models.
  • Verified 115 requirements in ModelSim.

Generic VSCF: Worked on verifying a military-based generator control unit design.

  • Developed Inter-FPGA, ADC, and Inter-LRU BFM models.
  • Developed the verification environment and integrating eNVM.
  • Verified 272 requirements in ModelSim, uncovering 81 design issues

Fpga Engineer

L&T Technology Services
01.2017 - 02.2019

This company is a service-based company, and I worked as a FPGA design and Verification engineer.

Parallel Port for PC-Printer Communication: Designed and verified a register control interface for PC-Printer communication via CPLD and IMX6U microprocessor for Caterpillar.

  • Conducted RTL coding in VHDL for design and testbench.
  • Executed functional verification using Modelsim.
  • Optimized design for new target CPLD (from MAX-II to MAX V).

ASIC Prototyping: Designed and tested the internal RAM of an ASIC chip on a Xilinx Virtex Ultrascale board for Intel.

  • Validated startup scripts for the Prototyping Kit.
  • Altered memory values as per requirements and power consumption report from Xilinx.
  • Introduced pipeline to the design based on throughput response.

Ethernet Extender: Designed, implemented, and demonstrated an Ethernet extender Channel full duplex bit communication system.

  • Conducted system testing using Vivado hardware manager and ILA (Chipscope).
  • Developed various modules in Verilog, including random wait and gap inducer modules.
  • Integrated RGMII interface between PHY chip and FPGA.
  • Developed a module for configuring the 88e1116r PHY chip, and conducted functional verification using Verilog testbench.

Education

Embedded Systems

Curtin University
Perth, WA
11.2023

Bachelor of Engineering - Electronics And Communications Engineering

K.N.S Institute of Technology
Bengaluru, India
01.2016

Skills

  • Embedded C (Arduino and nRF SDK)
  • Verilog
  • VHDL
  • UVMF
  • Communication protocols used: MQTT, SPI, UART and Ethernet
  • NRF5 SDK and nRF mesh SDK
  • FPGA front-end Design
  • DO- 254 Verification and Validation
  • Digital Circuits
  • FSM-based design
  • RTL Coding, optimizations, Synthesis, Simulation, Clock Domain Crossing, Static Timing Analysis (STA), Debugging & code coverage
  • Bluetooth Low Energy

Accomplishments

  • Verified and improved aerospace-based Universal Input Output bridge systems using DO-254 compliant test-benches, enhancing validation processes.
  • Led the successful verification of a military-based on-ground generator monitor, strengthening system reliability.
  • Played a pivotal role in designing a verification environment for advanced military generator control unit designs, leading to the identification of critical design issues.

Certification

  • Synthesis of digital systems, Jan 2018, Apr 2018, National Programme on Technology
  • Optimization of digital systems, Feb 2018, Mar 2018, National Programme on Technology

Temporary Employment

Sessional Academic 08/2022 - 11/2023

Curtin University, Perth, Australia

  • Coordinated Lab activities for the Computer Systems unit, wireless data networks and data network security at Curtin university for Bachelor students.
  • Clarified and solved the doubts and issues faced by students in the lab.
  • Invigilated the final lab exams. Responsible for marking the exams and posting results on the blackboard software.


Academic teacher 11/2023 - Present

Curtin College, Perth, Australia

  • Unit Coordinator, lecturer and lab tutor for Regression and Non-parametric Inference subject.
  • Lecturer and lab tutor for Computing, Robotics, and Future Technologies (Arduino) subject.
  • Tutor and lab instructor for Electrical Systems subject.

Visa

485 (Post study work stream)

References

  • Nazanin Mohammadi, Senior Lecturer, Curtin University, 08 9266 4727, N.Mohammadi@curtin.edu.au
  • Shivakant R Prajapati, Senior Lead Engineer, Collins Aerospace, +919867216189, shivakant.rp@gmail.com

Projects

Canny edge detection: The aim is to implement a canny edge detector algorithm in verilog.

  • RTL coding in verilog of canny operator
  • RTL coding in verilog of sobel operator
  • Development of testbench in Verilog


Spiking Neural Network (Dr. Marco Winzker): The aim is to understand Dr. Marco’s implementation of Spiking Neural Networks (SNN) and their use in the detection of yellow and blue colors of an image. 

  • Understanding the VHDL code of the SNN implementation and converting it to Verilog
  • Development of testbench in Verilog

Hobbies: Pencil sketching

I spend my free time sketching with pencils. I like to draw different things, including stuff I find online. Sketching helps me get better at noticing small details and it's also a calm activity that helps me be patient and focused. When I sketch, it's my way of taking time for myself and being committed to something I enjoy.

Languages

English
Full Professional
Hindi
Full Professional
Rahul Siddalingappa