Samuel Tensingh
Sydney
Summary
Experienced Digital Backend Engineer and Doctoral Researcher at The University of Sydney, specializing in ASIC design and digital electronics. Possessing a solid background in semiconductor design from 15+ years of work at renowned companies like ST Microelectronics, Broadcom, and Macquarie University. Actively involved as an IEEE Senior Member, driving innovation in Neuromorphic computing and digital circuit design to bridge the gap between academia and industry.
Overview
11
11
years of professional experience
1
1
Certification
Work History
Digital Backend Engineer
Macquarie University
01.2025 - Current
- Establishing the IC design flow in the Silicon Platforms lab and implementing physical design solutions for high-performance digital systems.
- Working closely with the digital design team to develop high-speed custom design solutions and fostering industrial collaborations in Australia.
Associate Lecturer
University of Sydney
08.2023 - 08.2024
- Taught a Digital Design Implementation micro-credential course in New South Wales, offered by the University of Sydney, S3B, WPCA, and Cadence.
- Led hands-on sessions using Cadence tools (Genus, Innovus, Tempus, and Conformal) and developed assessments on RTL synthesis and RISC CPU implementation.
Senior Physical Design Engineer
ST Microelectronics
02.2017 - 10.2022
- Managed Place and Route, Physical Verification, and Redhawk analysis for 40nm security-focused digital ICs
- Presented award-winning research at SNUG Penang 2018 and ST Microelectronics Forum 2022
- Published an article in Singapore Semiconductor Voice (2019) and MDPI Electronics
- Attended a technical workshop at STM Design Centre, Grenoble
Senior Physical Design Engineer
Broadcom Limited
02.2016 - 12.2016
- Executed P&R (block build) using ICCII for a 10nm ASIC test chip
- Optimized buffer placements for skew matching, earning recognition for timely block delivery to the IP team
Senior Physical Design Engineer
Avago Technologies
05.2014 - 02.2016
10nm ASICs: Led a P&R block build team collaborating on ICCII experiments, and received a spot award for testing the 10nm ICCII P&R flow.
28nm ASICs: Achieved timing closure across 60 corners for SerDes IP, optimized clock skew and managed P&R, physical verification, and STA for five blocks with up to 100 macros.
40nm ASICs: Led many teams in block-level P&R, and performed chip-level power analysis and conformal verification. Managed floor planning, CTS, routing, STA, and verification across multiple blocks, including a 4M-gate standard cell block, pad blocks, and a PLL wrapper. Designed two standard cell blocks with over 150 macros.
Education
PhD - Biomedical Engineering
University of Sydney
12-2027
Post Graduate Program - AI and Machine Learning: Business Applications
The McCombs School of Business
02.2024
MBA -
Anglia Ruskin University
02.2012
BE - Electronics and Communication
Anna University
04.2008
Skills
- Digital ASIC Design
- Digital Electronics
- Neuromorphic Circuit Design
- EDA tools
- Technical Communication Expert
- Team Leadership
Membership
- Senior Member of IEEE (SMIEEE)
- Senior Member of International Economics Development Research Center (IEDRC), Hong Kong
- Senior Member of The Institution of Engineers of Singapore (Sr.MIES)
- Member of Engineers Australia (MIEAust)
- Member of the Teacher's Guild of NSW, Australia (MTGN)
- Member of the Australasian Association for Engineering Education (AAEE)
- Member of the Royal Society of New South Wales, Australia
- Member of Engineering New Zealand (MEngNZ)
- Member of the Virtual Physiological Human Institute for Biomedical Research, Belgium
- Member of Engineers Ireland (MIEI)
- Member of The Institution of Engineering and Technology (MIET), UK
- Member of the Institution of Engineering Designers (MIED), UK
- Member of the European Society of Engineering Education (SEFI)
- Member of the American Society for Engineering Education (ASEE)
- Member of the American Society for Engineering Management (ASEM)
- Member of the National Society of Professional Engineers (NSPE), USA
- Member of the Association for Computing Machinery (ACM), USA
- Member of The Institute of Electronics, Information and Communication Engineers (IEICE), Japan
- Member of The International Association of Engineers (IAENG), Hong Kong
- Member of the Singapore Semiconductor Industry Association (SSIA)
Certification
- System C Language Fundamentals v12.2, 01/01/24
- Verilog Language and Application v27.0, 01/01/24
- Digital IC Design Fundamentals v2.0, 01/01/24
- C++ Language Fundamentals v21.03, 01/01/24
- Basic Static Timing Analysis v2.0, 01/01/23
- Genus Synthesis Solution with Stylus Common UI v22.1, 01/01/23
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI v22.1, 01/01/23
- Innovus Block Implementation with Stylus Common UI v22.1, 01/01/23
- Conformal Low Power Verification Using IEEE 1801 v22.1, 01/01/23
- Conformal Equivalence Checking v22.1, 01/01/23
- Cadence RTL – to – GDSII Flow v4.0, 01/01/23
- Genus Low Power Synthesis Flow with IEEE 1801 v22.1, 01/01/23
- Fundamentals of IEEE 1801 Low–Power Specification Format v10.0, 01/01/23
- Advanced Synthesis with Genus Stylus Common UI v22.1, 01/01/23
- Cerebrus Intelligent Chip Explorer v22.1, 01/01/23
- Artificial Intelligence and Machine Learning Fundamentals v1.0, 01/01/23
- Design for Test Fundamentals v2.0, 01/01/23
- Innovus Implementation System (Hierarchical) v19.1, 01/01/20
Patents
- 06/01/22, Systems for remote monitoring and diagnostics of cyber/network security through machine learning, Germany
- 02/01/23, IoT-based drainage pipes cleaning robot system, South Africa
- 03/01/23, IoT-based agricultural drone for pesticide spray, UK
- 04/01/23, Intelligent charging station based on Internet of Things, Germany
- 06/01/23, Intelligent device for crime scene investigation, UK
- 06/01/23, IoT-based street cleaning vehicle, UK
Certification Statement
I certify that the information provided in this resume is true and accurate to the best of my knowledge.
Timeline
Digital Backend Engineer
Macquarie University
01.2025 - Current
Associate Lecturer
University of Sydney
08.2023 - 08.2024
Senior Physical Design Engineer
ST Microelectronics
02.2017 - 10.2022
Senior Physical Design Engineer
Broadcom Limited
02.2016 - 12.2016
Senior Physical Design Engineer
Avago Technologies
05.2014 - 02.2016
PhD - Biomedical Engineering
University of Sydney
Post Graduate Program - AI and Machine Learning: Business Applications
The McCombs School of Business
MBA -
Anglia Ruskin University
BE - Electronics and Communication
Anna University
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