Sarveshwaran Senthilkumar
Docklands,VIC
Summary
Motivated Master's student in Electrical Engineering at RMIT university, with a strong foundation in circuit design and analysis. Proficient in tools such as MATLAB, Simulink, Homer and AutoCAD. Seeking an internship opportunity in Australia to apply academic knowledge and gain hands-on experience in the industry.
Overview
1
1
year of professional experience
Work History
Design Verification Engineer
Smart DV
07.2023 - 02.2024
A Smart DV Design Engineer typically works in the design, verification, and development of digital and analog systems, focusing on aspects such as System-on-Chip (SoC) verification, FPGA development, and ASIC design
Education
MASTER(Current) - Electrical Engineering
RMIT University
Melbourne, VIC05-2026
Bachelor of Engineering - Electronic And Communications Engineering
Mepco Schlenk Engineering College
Tamil Nadu ,India04-2023
Skills
- Circuit design
- Microsoft PowerPoint
- PCB layout design(easyEDA)
- Digital electronics
- AUTOCAD Electrical software
- MATLAB proficiency
- Verilog programming
- Homer pro
Timeline
Design Verification Engineer
Smart DV
07.2023 - 02.2024
MASTER(Current) - Electrical Engineering
RMIT University
Bachelor of Engineering - Electronic And Communications Engineering
Mepco Schlenk Engineering College
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